1. Field of the Invention
The present invention generally relates to the field of patterned structures, and more particularly, to a method for fabricating a patterned structure in a semiconductor device.
2. Description of the Prior Art
Integrated circuits (IC) are made of devices and interconnections, which are formed through patterned features in different layers. During the fabrication process of ICs, the photolithography is an essential technique. The photolithography is used to form designed patterns, such as implantation patterns or layout patterns, on at least a photomask, and then to precisely transfer such patterns to a photoresist layer by exposure and development steps. Finally, by performing several semiconductor processes such as etching process, ion implantation, deposition and so forth, complicated and sophisticated IC structures can be obtained.
With the continuous miniaturization of semiconductor devices and the remarkable advance in fabrication techniques of semiconductor devices, the conventional lithography process meets its limitation due to printability and manufacturability problems. To meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, a double patterning technique (DPT) has been developed and taken as one of the most promising lithographic technologies for 32 nanometer (nm) node and 22 nm node patterning, since it can increase the half-pitch resolution up to twice higher by using current infrastructures. For example, the litho-etch-litho-etch (LELE) approach, also called 2P2E, is one of the most common DPTs for fabricating patterns in a semiconductor device. When a 2P2E approach is carried out, a target layer, such as a polysilicon layer, located on a substrate will first be covered with an etch mask in order to define regions for forming patterns. Then, a plurality of stripe patterned target layers, which are parallel to each other, are formed by performing the first litho-etch process. In this way, critical dimension (CD) is defined between two adjacent stripe patterned target layers. Finally, a second litho-etch process is performed in order to cut out or split a portion of the stripe patterned target layers. Through the preceding processes, structures with relatively high resolution can be obtained. However, there are still many drawbacks that need to be overcome. For example, the CD between two adjacent stripe patterned target layers is further enlarged during the second litho-etch process, which may lead to inevitable dimension variation. Since there is a strong link between CD and electrical properties of the semiconductor device, the CD in semiconductor devices should be well controlled so as to increase the performance and the reliability of the semiconductor device.
Accordingly, in order to overcome the above-mentioned drawbacks, there is a need to provide a modified method of fabricating a patterned structure with improved reliability.